1. Technical Field
The present invention relates to a transmission system, a transmitter, a receiver, and a transmission method. More particularly, the present invention relates to a transmission system, a transmitter, a receiver and a transmission method for transmitting serial data by using a clock signal.
2. Related Art
A known transmission system performs wired/wireless/optical transmission of serial data sequences by using a clock signal. A transmitter for use in serial data transmission outputs a data signal to be transmitted based on an original data sequence by using the edge timing of a clock signal. A receiver samples the received data signal at the edge timing of a clock signal which is synchronized with the data signal, to read the original data sequence. Here, when there is a difference in edge timing between the clock signal and data signal received by the receiver, the received data sequence may have bit errors.
There are mainly two different methods to enable the receiver to obtain a clock signal which is synchronized with the received data signal. According to one of the methods, the clock signal used by the transmitter to generate the data signal is transmitted to the receiver in parallel with the data signal via a different transmission path from the data signal. The receiver thus receives the clock signal which is used for the transmission. According to the other method, the transmitter generates the data signal by embedding the clock signal into the original data sequence, and transmits the generated data signal. In this case, the receiver recovers the clock signal from the received data signal, and uses the recovered clock signal.
The former method has the following problem. Jitter (hereinafter referred to as “deterministic jitter”) is generated in the data signal received by the receiver depending on the characteristics of the transmission path, since the data signal has irregular occurrences of the edge timings. On the other hand, such deterministic jitter depending on the characteristics of the transmission path is hardly generated in the clock signal since the clock signal has a regular interval between adjacent edge timings. Therefore, according to the former method, a difference in timing is generated in correspondence with the difference in amount of deterministic jitter between the data signal and clock signal which are received by the receiver. This timing difference is not corrected. Therefore, when the former method is employed, bit errors may occur at the receiver due to the deterministic jitter injected to the data sequence received by the receiver.
The latter method also has a problem. The receiver has a phase locked loop (PLL) circuit which performs feedback control to cause the edge timing of the data signal received by the receiver to be synchronized with the edge timing of the clock signal recovered by the receiver. The PLL circuit includes therein a phase detector, a loop filter, and a frequency-variable oscillator.
Here, as long as the frequency of the jitter injected to the data signal falls within the loop bandwidth of the loop filter, the phase of the clock signal is varied in accordance with the jitter injected to the data signal. If this is the case, the difference in timing between the data signal and clock signal is reduced, and the bit errors can be thus prevented. However, when the frequency of the jitter injected to the data signal takes a value outside the loop bandwidth, the phase of the clock signal can not be varied in accordance with the jitter injected to the data signal. In this case, there is a difference in timing between the data signal and clock signal, and bit errors may therefore occur.
Here, when the successive logical values of the data signal received by the receiver are the same, the received data signal does not have an edge. Therefore, the receiver relating to the latter method can not perform feedback control. In this case, the receiver relating to the latter method can not adjust the timing difference between the received data signal and the recovered clock signal, and therefore can not reduce the bit errors. Furthermore, since the receiver relating to the latter method includes therein a PLL circuit or the like, the receiver requires more complicated circuits and more advanced design techniques than the receiver relating to the former method. As a result, the receiver relating to the latter method requires a larger area for the circuits and a higher cost.